[SharpMZ] Zkouseni pridavnych karet pro MZ-2500
Michal Medek
Michal.Bruntal na seznam.cz
Støeda Kvìten 31 20:33:02 CEST 2017
Ahoj,"
zakladam toto vlakno pro sdileni zkusenosti se $subj. Chtel bych diskutovat
poznatky/problemy/zkusenosti se stavbou/testovanim/provozem. Proste vse. co
by pomohlo k jejich pouziti.
1) K pametovym kartam jsem zjistil
Memory Mapping Register
address R / W Description
B4h W
Bit 7 6 5 4 3 2 1 0
signal
MRSEL
Select the memory mapping register to be read and written in B5hÂ
After reading / writing B5h, the value of B4h is autoincremented
MRSEL Memory address MRSEL Memory address
0 0000h - 1FFFh 4 8000h - 9FFFh
1 2000h - 3FFFh 5 A000h - BFFFh
2 4000h - 5FFFh 6 C000h - DFFFh
3 6000h - 7FFFh 7 E000h - FFFFh
B5h R / W
Bit 7 6 5 4 3 2 1 0
signal
MB
Memory block number to allocate
MB Memory block Weight when accessing
00h - 0Fh Main RAM (8K × 16 = 128K) On M1 cycle + 1
10 h - 1 Fh Extended RAM (8 K × 16 = 128 K) On M1 cycle + 1
20 h - 27 h Standard graphic VRAM (B / R / G / I) +1Â (*)
28 h - 2 Fh Extended graphic VRAM (B / R / G / I) +1Â (*)
30 h - 31 h Standard graphic VRAM (Read Modify Write) +2Â (*)
32 h - 33 h Extended graphic VRAM (Read Modify Write) +2Â (*)
34h-37h IPL ROM On M1 cycle + 1
38h Text VRAM +1Â (*)
39h Kanji ROM / PCG +2Â (*)
3Ah Dictionary ROM ???
3 Ch-3 Fh Communication ROM On M1 cycle + 1
(*) M1 cycle impossible · When accessing during the display period, wait
until the blanking period separately takes effect
According to
(https://translate.googleusercontent.com/translate_c?act=url&depth=1&hl=cs&ie=UTF8&prev=_t&rurl=translate.google.cz&sl=ja&sp=nmt4&tl=en&u=http://x1center.org/&usg=ALkJrhishUfFNT5Smi5Yi0lE0nO-d3QtPw)
 the survey of the X1 center
(https://translate.googleusercontent.com/translate_c?act=url&depth=1&hl=cs&ie=UTF8&prev=_t&rurl=translate.google.cz&sl=ja&sp=nmt4&tl=en&u=http://x1center.org/&usg=ALkJrhishUfFNT5Smi5Yi0lE0nO-d3QtPw)
 , the CPU accessible period of the graphic VRAM is 24 KHz: memory write
cycle + 50 clock + memory write cycle 15 KHz: memory write cycle + 91 clock
+ memory write cycle Normal access · additional weight by the read modify
write They are + 1 and + 2, respectively, but the above values ​​do not
change
Slo by tedy vyzkouset zapsat na MemoryBlock (cislo bloku), pak na
MemorySelect (cislo banky) a zapsat par byte (ne pro ROM) a pak je stejnym
zpusobem precist.
Vysledkem by mohlo byt zjisteni, ze to tak funguje a ze pridavne karty
funguji. Nasledne otestovat, ze jsme vyrobili repliky dobre a ze funguji.
2)Â
Graphics controller internal registers
register Description
00h Pattern register B
01h Pattern register R
02h The pattern register G
03h Pattern register I
04h Color register
Bit 7 6 5 4 3 2 1 0
signal
I G R B
05h Function register / screen selection register
Bit 7 6 5 4 3 2 1 0
signal FN
I G R B
FN function 00: REPLACEÂ
01: PSETÂ
10: Clear screen
I / G / R / B Drawing plane selection 0: Do not drawÂ
1: Draw
REPLACE
For each plane specified only for the plane specified by the screen
selection register (05h) to be rewritten,
1. AND the VRAM data and the value obtained by inverting the value of the
bit mask register
2. OR ((CPU write data AND pattern register AND bit mask register
register value) is ORed only for the plane specified by the color
register (04h)
3. Write results to VRAM
(An image that punctures the VRAM with the bit mask register value and
inserts the cut-out pattern with the CPU write value)
PSET
For each plane specified only for the plane specified by the screen
selection register (05h) to be rewritten,
1. AND the VRAM data and the inverted value of the CPU write data
2. Only the plane specified by the color register (04h), OR (CPU write
data AND pattern register) is ORed
3. Write results to VRAM
(Image in which hole is drilled in VRAM with CPU write value and fit pattern
fitting there)
06h Bit mask register
07h Select read control register
Bit 7 6 5 4 3 2 1 0
signal
0
A
1 I G R B
A Direct Read Read Plane 00: BÂ
01: RÂ
10: GÂ
11: I
I / G / R / B Select read specification color
08h, 09h Display area vertical direction start line setting
Port 09h 08h
Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
signal
GDEVS
Specify the number of rasters in 9 bitsÂ
0 to 190 h (vertical 400 lines)Â
0 to C 8 h (length 200 lines)Â
0Ah, 0Bh Display area vertical direction end line setting
Port 0 Bh 0 Ah
Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
signal
GDEVE
Like GDEVS
0Ch Display area horizontal direction start setting
Bit 7 6 5 4 3 2 1 0
signal
GDEHS
0 to 50 hÂ
Horizontal 640 dots 8 dots Unit 320 dots 4 dots unit
0Dh Display area horizontal direction stop setting
Bit 7 6 5 4 3 2 1 0
signal
GDEHE
Same as GDEHS
0Eh Display mode switching
Bit 7 6 5 4 3 2 1 0
signal EX 0 0 4C 256C V200 H640 PRI
EX Standard VRAM / Extended VRAM Selection 0: Standard VRAMÂ
1: Extended VRAM
4C 4 color modeÂ
(Only in 640 x 400 mode) 0: 4 color modeÂ
1: 16 color or 256 color mode
256C 256 colors (8 planes simultaneous output) mode 0: 16 color modeÂ
1: 256 color mode
V200 Number of vertical lines 0: 400 lineÂ
1: 200 line
H640 Number of horizontal dots 0: 320 dotsÂ
1: 640 dots
PRI Priority when overlapping two screensÂ
(320 x 200 only in 16 color mode ·Â
Specify 1 in other modes) 0: Young screen with the number at the backÂ
1: Young number screen is toward you
0Fh Horizontal dot scroll amount within the scroll area
Bit 7 6 5 4 3 2 1 0
signal
HSCRL
Horizontal scroll amount 0 to 7 in 1 dot unitÂ
A specified number of white pixels are inserted from the left edge of the
screen, and the screen shifts to the right by that amount (scrolls)Â
Therefore, it is necessary to hide the left end from the display areaÂ
In 320x200 2 screen mode and 256 color mode, this function can be used only
for screens 0 and 2, so it is practically impossible to scroll smoothly
10h, 11h Top left address of screen
Port 11h 10 h
Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
signal
SAD 0
12h, 13h Scroll wrapping address
Port 13h 12h
Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
signal
SAD 1
When the CRTC's VRAM read address counter reaches this address, the address
counter returns to 0000h from the next read
14h, 15h Display address after scroll end line
Port 15 h 14h
Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
signal
SAD 2
When the display raster reaches the scroll end line, display starts from
this address
16h, 17h Scroll end line
Port 17h 16h
Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
signal
SL1
0 to 190 h (vertical 400 lines)Â
0 to C 8 h (length 200 lines)Â
18h Screen display register
Bit 7 6 5 4 3 2 1 0
signal I1 G1 R1 B1 I 0 G 0 R 0 B 0
A plane with a bit of 1 is displayed
----------------------------------------------------------------------------
Zajimavy registr 0Eh pro zmenu rezimu. Chtelo by to vyzkouset s ohledem na
vyuzivani pameti a efektu na vystupu
3) PALETE karta/registr.
OPN GPIO
SSG register R / W Description
07h W I / O setting of I / O ports A and B
Bit 7 6 5 4 3 2 1 0
signal IOB IOA noise tone
IOB I / O port B input / output 0: InputÂ
1: Output
IOA I / O port A input / output 0: InputÂ
1: Output
For MZ - 2500, set port A as output and port B as input
0Eh W I / O port A
Bit 7 6 5 4 3 2 1 0
signal VACL VOE VBUSY VDATA MOUSE PLT DRSEL READYA
VACL Voice board reset bit 0: Normal operationÂ
1: Reset the voice board
VOE Voice board ROM specification 0: Internal ROMÂ
1: External ROM
VBUSY Voice board handshake bit
VDATA Voice board transmission data
MOUSE SIO B channel function selection 0: RS-232C (9 pin)Â
1: Mouse
PLT 4096 color palette board output selection 0: 4096 color Palette board
Select outputÂ
1: Select main unit output
The DRSEL FDD drive number change 0: Built-in FDD is 0, 1 / external FDD is
2, 3Â
1: External FDD is 0, 1 / Built-in FDD is 2, 3
READYA RS-232C RR signal (D-Sub 25 pin connector No. 11 pin)
0Fh R I / O port B
Bit 7 6 5 4 3 2 1 0
signal VACK RASTER 80B 2000 ALARM CDB CIA CDA
VACK Acknowledge from voice board
RASTER Display output mode 0: 400 lines (24 kHz)Â
1: 200 lines (15 kHz)
80B MZ-80B mode 0: 80 B mode
2000 MZ-2000 mode 0: 2000 mode
ALARM RTC ALARM output
CDB RS-232C CD signal (D-Sub 9 pin connector 9 pin)
CIA RS-232C CI signal (D-Sub 25 pin connector No. 22 pin)
CDA RS-232C CD signal (D-Sub 25 pin connector No. 8 pin)
Zajimavy registr 0Eh bit PLT, ktery zapina podporu 4096 barev
4096 color palette board
16 bit I / O access required
address R / W Description
AEh W 4096 color palette
Address [15: 8]
Bit 15 14 13 12 11 Ten 9 8
signal
PALNO G /Â R B
G /Â RB 0: DATA [3: 0] is written in the blue component of the pallet number
PALNO, and DATA [7: 4] is written in the red componentÂ
1: Write DATA [3: 0] to the green component of the pallet number PALNO
The validity / invalidity of the pallet board is controlled by the OPO IOA
[2]
A pak tady zapisovat do registru PALNO cislo barvy G a RB a pak jeji hodnotu
4) Mel by nekdo schema a/nebo fotky teto pridavne karty? Ze by se mohla
casem pripravit a vyrobit replika. samozrejme by to chtelo mit v MZ-2500 ten
pridavny domecek, ktery by se mohl taky replikovat.
MZ-1 R 37 640 K EMM
16 bit I / O access required
address R / W Description
ACh W Write address latchÂ
EMM address [19: 16] = {A15 - A8}, EMM address [15: 8] = {D7 - D0}
ADh R Reading dataÂ
EMM address [7: 0] = {A15 - A8}, data = {D7 - D0}
W Write dataÂ
EMM address [7: 0] = {A15 - A8}, data = {D7 - D0}
* There is no auto increment of the address
Tak to bylo pro definovani par takovych bodu, kterymi by jsme se mohli
zabyvat a urceni mista, kde je sdilet.
Mikes
"
------------- dal¹í èást ---------------
HTML pÅ™Ãloha byla odstranÄ›na...
URL: http://mail.ordoz.com/pipermail/sharpmz/attachments/20170531/ea6347ce/attachment-0001.html
Dal¹í informace o konferenci SharpMZ