<html><body>Ahoj,<blockquote data-email="Michal.Bruntal@seznam.cz"><div><br></div><div>zakladam toto vlakno pro sdileni zkusenosti se $subj. Chtel bych diskutovat poznatky/problemy/zkusenosti se stavbou/testovanim/provozem. Proste vse. co by pomohlo k jejich pouziti.</div><div>1) K pametovym kartam jsem zjistil</div><div><h3 style="color:rgb(0,0,0);font-family:'Times New Roman'"><span>Memory Mapping Register</span></h3><table style="font-family:'Times New Roman'" cellpadding="2" border="1"><tbody><tr bgcolor="#CCBBBB"><th><span>address</span></th><th><span>R / W</span></th><th><span>Description</span></th></tr><tr><td align="center"><span>B4h</span></td><td align="center"><span>W</span></td><td><table cellspacing="0" cellpadding="2" border="1"><tbody><tr bgcolor="#CCBBBB" align="center"><th><span>Bit</span></th><td><span>7</span></td><td><span>6</span></td><td><span>5</span></td><td><span>4</span></td><td><span>3</span></td><td><span>2</span></td><td><span>1</span></td><td><span>0</span></td></tr><tr align="center"><th bgcolor="#CCBBBB"><span>signal</span></th><td colspan="5" bgcolor="lightgray"><br></td><td colspan="3"><span>MRSEL</span></td></tr></tbody></table><span>Select the memory mapping register to be read and written in B5h </span><br><span>After reading / writing B5h, the value of B4h is autoincremented</span><table cellspacing="0" cellpadding="2" border="1"><tbody><tr bgcolor="#FFFFEE"><th><span>MRSEL</span></th><th><span>Memory address</span></th><th><span>MRSEL</span></th><th><span>Memory address</span></th></tr><tr><td align="center"><span>0</span></td><td><span>0000h - 1FFFh</span></td><td align="center"><span>4</span></td><td><span>8000h - 9FFFh</span></td></tr><tr><td align="center"><span>1</span></td><td><span>2000h - 3FFFh</span></td><td align="center"><span>5</span></td><td><span>A000h - BFFFh</span></td></tr><tr><td align="center"><span>2</span></td><td><span>4000h - 5FFFh</span></td><td align="center"><span>6</span></td><td><span>C000h - DFFFh</span></td></tr><tr><td align="center"><span>3</span></td><td><span>6000h - 7FFFh</span></td><td align="center"><span>7</span></td><td><span>E000h - FFFFh</span></td></tr></tbody></table></td></tr><tr><td align="center"><span>B5h</span></td><td align="center"><span>R / W</span></td><td><table cellspacing="0" cellpadding="2" border="1"><tbody><tr bgcolor="#CCBBBB" align="center"><th><span>Bit</span></th><td><span>7</span></td><td><span>6</span></td><td><span>5</span></td><td><span>4</span></td><td><span>3</span></td><td><span>2</span></td><td><span>1</span></td><td><span>0</span></td></tr><tr align="center"><th bgcolor="#CCBBBB"><span>signal</span></th><td colspan="2" bgcolor="lightgray"><br></td><td colspan="6"><span>MB</span></td></tr></tbody></table><small><br></small><span>Memory block number to allocate</span><table cellspacing="0" cellpadding="2" border="1"><tbody><tr bgcolor="#FFFFEE"><th><span>MB</span></th><th><span>Memory block</span></th><th><span>Weight when accessing</span></th></tr><tr><td><span>00h - 0Fh</span></td><td><span>Main RAM (8K × 16 = 128K)</span></td><td><span>On M1 cycle + 1</span></td></tr><tr><td><span>10 h - 1 Fh</span></td><td><span>Extended RAM (8 K × 16 = 128 K)</span></td><td><span>On M1 cycle + 1</span></td></tr><tr><td><span>20 h - 27 h</span></td><td><span>Standard graphic VRAM (B / R / G / I)</span></td><td><span>+1 <small>(*)</small></span></td></tr><tr><td><span>28 h - 2 Fh</span></td><td><span>Extended graphic VRAM (B / R / G / I)</span></td><td><span>+1 <small>(*)</small></span></td></tr><tr><td><span>30 h - 31 h</span></td><td><span>Standard graphic VRAM (Read Modify Write)</span></td><td><span>+2 <small>(*)</small></span></td></tr><tr><td><span>32 h - 33 h</span></td><td><span>Extended graphic VRAM (Read Modify Write)</span></td><td><span>+2 <small>(*)</small></span></td></tr><tr><td><span>34h-37h</span></td><td><span>IPL ROM</span></td><td><span>On M1 cycle + 1</span></td></tr><tr><td><span>38h</span></td><td><span>Text VRAM</span></td><td><span>+1 <small>(*)</small></span></td></tr><tr><td><span>39h</span></td><td><span>Kanji ROM / PCG</span></td><td><span>+2 <small>(*)</small></span></td></tr><tr><td><span>3Ah</span></td><td><span>Dictionary ROM</span></td><td><span>???</span></td></tr><tr><td><span>3 Ch-3 Fh</span></td><td><span>Communication ROM</span></td><td><span>On M1 cycle + 1</span></td></tr></tbody></table><p><span><small>(*)</small> M1 cycle impossible · When accessing during the display period, wait until the blanking period separately takes effect</span></p><p><span><a href="https://translate.googleusercontent.com/translate_c?act=url&depth=1&hl=cs&ie=UTF8&prev=_t&rurl=translate.google.cz&sl=ja&sp=nmt4&tl=en&u=http://x1center.org/&usg=ALkJrhishUfFNT5Smi5Yi0lE0nO-d3QtPw">According to</a> the survey of the <a href="https://translate.googleusercontent.com/translate_c?act=url&depth=1&hl=cs&ie=UTF8&prev=_t&rurl=translate.google.cz&sl=ja&sp=nmt4&tl=en&u=http://x1center.org/&usg=ALkJrhishUfFNT5Smi5Yi0lE0nO-d3QtPw">X1 center</a> , the CPU accessible period of the graphic VRAM is 24 KHz: memory write cycle + 50 clock + memory write cycle 15 KHz: memory write cycle + 91 clock + memory write cycle Normal access · additional weight by the read modify write They are + 1 and + 2, respectively, but the above values do not change</span></p></td></tr></tbody></table></div><div><br></div><div>Slo by tedy vyzkouset zapsat na MemoryBlock (cislo bloku), pak na MemorySelect (cislo banky) a zapsat par byte (ne pro ROM) a pak je stejnym zpusobem precist.</div><div>Vysledkem by mohlo byt zjisteni, ze to tak funguje a ze pridavne karty funguji. Nasledne otestovat, ze jsme vyrobili repliky dobre a ze funguji.</div><div><br></div><div>2) </div><div><h4 style="font-family:'Times New Roman';font-size:medium"><span>Graphics controller internal registers</span></h4><table style="font-family:'Times New Roman'" cellpadding="2" border="1"><tbody><tr bgcolor="#CCBBBB"><th><span>register</span></th><th><span>Description</span></th></tr><tr><td align="center"><span>00h</span></td><td><span>Pattern register B</span></td></tr><tr><td align="center"><span>01h</span></td><td><span>Pattern register R</span></td></tr><tr><td align="center"><span>02h</span></td><td><span>The pattern register G</span></td></tr><tr><td align="center"><span>03h</span></td><td><span>Pattern register I</span></td></tr><tr><td align="center"><span>04h</span></td><td><span>Color register</span><table cellspacing="0" cellpadding="2" border="1"><tbody><tr bgcolor="#CCBBBB" align="center"><th><span>Bit</span></th><td><span>7</span></td><td><span>6</span></td><td><span>5</span></td><td><span>4</span></td><td><span>3</span></td><td><span>2</span></td><td><span>1</span></td><td><span>0</span></td></tr><tr align="center"><th bgcolor="#CCBBBB"><span>signal</span></th><td colspan="4" bgcolor="lightgray"><br></td><td><span>I</span></td><td><span>G</span></td><td><span>R</span></td><td><span>B</span></td></tr></tbody></table></td></tr><tr><td align="center"><span>05h</span></td><td><span>Function register / screen selection register</span><table cellspacing="0" cellpadding="2" border="1"><tbody><tr bgcolor="#CCBBBB" align="center"><th><span>Bit</span></th><td><span>7</span></td><td><span>6</span></td><td><span>5</span></td><td><span>4</span></td><td><span>3</span></td><td><span>2</span></td><td><span>1</span></td><td><span>0</span></td></tr><tr align="center"><th bgcolor="#CCBBBB"><span>signal</span></th><td colspan="2"><span>FN</span></td><td colspan="2" bgcolor="lightgray"><br></td><td><span>I</span></td><td><span>G</span></td><td><span>R</span></td><td><span>B</span></td></tr></tbody></table><small><br></small><table cellspacing="0" cellpadding="2" border="1"><tbody><tr><th bgcolor="#FFFFEE"><span>FN</span></th><td><span>function</span></td><td><span>00: REPLACE </span><br><span>01: PSET </span><br><span>10: Clear screen</span></td></tr><tr><th bgcolor="#FFFFEE"><span>I / G / R / B</span></th><td><span>Drawing plane selection</span></td><td><span>0: Do not draw </span><br><span>1: Draw</span></td></tr></tbody></table><small><br></small><dl><dt><span><b>REPLACE</b></span></dt><dd><span>For each plane specified only for the plane specified by the screen selection register (05h) to be rewritten,</span><ol><li><span>AND the VRAM data and the value obtained by inverting the value of the bit mask register</span></li><li><span>OR ((CPU write data AND pattern register AND bit mask register register value) is ORed only for the plane specified by the color register (04h)</span></li><li><span>Write results to VRAM</span></li></ol><span>(An image that punctures the VRAM with the bit mask register value and inserts the cut-out pattern with the CPU write value)</span></dd><dt><span><b>PSET</b></span></dt><dd><span>For each plane specified only for the plane specified by the screen selection register (05h) to be rewritten,</span><ol><li><span>AND the VRAM data and the inverted value of the CPU write data</span></li><li><span>Only the plane specified by the color register (04h), OR (CPU write data AND pattern register) is ORed</span></li><li><span>Write results to VRAM</span></li></ol><span>(Image in which hole is drilled in VRAM with CPU write value and fit pattern fitting there)</span></dd></dl></td></tr><tr><td align="center"><span>06h</span></td><td><span>Bit mask register</span></td></tr><tr><td align="center"><span>07h</span></td><td><span>Select read control register</span><table cellspacing="0" cellpadding="2" border="1"><tbody><tr bgcolor="#CCBBBB" align="center"><th><span>Bit</span></th><td><span>7</span></td><td><span>6</span></td><td><span>5</span></td><td><span>4</span></td><td><span>3</span></td><td><span>2</span></td><td><span>1</span></td><td><span>0</span></td></tr><tr align="center"><th rowspan="2" bgcolor="#CCBBBB"><span>signal</span></th><td colspan="3" bgcolor="lightgray"><br></td><td><span>0</span></td><td colspan="2" bgcolor="lightgray"><br></td><td colspan="2"><span>A</span></td></tr><tr align="center"><td colspan="3" bgcolor="lightgray"><br></td><td><span>1</span></td><td><span>I</span></td><td><span>G</span></td><td><span>R</span></td><td><span>B</span></td></tr></tbody></table><small><br></small><table cellspacing="0" cellpadding="2" border="1"><tbody><tr><th bgcolor="#FFFFEE"><span>A</span></th><td><span>Direct Read Read Plane</span></td><td><span>00: B </span><br><span>01: R </span><br><span>10: G </span><br><span>11: I</span></td></tr><tr><th bgcolor="#FFFFEE"><span>I / G / R / B</span></th><td colspan="2"><span>Select read specification color</span></td></tr></tbody></table></td></tr><tr><td align="center"><span>08h, 09h</span></td><td><span>Display area vertical direction start line setting</span><table cellspacing="0" cellpadding="2" border="1"><tbody><tr bgcolor="#CCBBBB" align="center"><th><span>Port</span></th><td colspan="8"><span>09h</span></td><td colspan="8"><span>08h</span></td></tr><tr bgcolor="#CCBBBB" align="center"><th><span>Bit</span></th><td><span>7</span></td><td><span>6</span></td><td><span>5</span></td><td><span>4</span></td><td><span>3</span></td><td><span>2</span></td><td><span>1</span></td><td><span>0</span></td><td><span>7</span></td><td><span>6</span></td><td><span>5</span></td><td><span>4</span></td><td><span>3</span></td><td><span>2</span></td><td><span>1</span></td><td><span>0</span></td></tr><tr align="center"><th bgcolor="#CCBBBB"><span>signal</span></th><td colspan="7" bgcolor="lightgray"><br></td><td colspan="9"><span>GDEVS</span></td></tr></tbody></table><span>Specify the number of rasters in 9 bits </span><br><span>0 to 190 h (vertical 400 lines) </span><br><span>0 to C 8 h (length 200 lines) </span><br></td></tr><tr><td align="center"><span>0Ah, 0Bh</span></td><td><span>Display area vertical direction end line setting</span><table cellspacing="0" cellpadding="2" border="1"><tbody><tr bgcolor="#CCBBBB" align="center"><th><span>Port</span></th><td colspan="8"><span>0 Bh</span></td><td colspan="8"><span>0 Ah</span></td></tr><tr bgcolor="#CCBBBB" align="center"><th><span>Bit</span></th><td><span>7</span></td><td><span>6</span></td><td><span>5</span></td><td><span>4</span></td><td><span>3</span></td><td><span>2</span></td><td><span>1</span></td><td><span>0</span></td><td><span>7</span></td><td><span>6</span></td><td><span>5</span></td><td><span>4</span></td><td><span>3</span></td><td><span>2</span></td><td><span>1</span></td><td><span>0</span></td></tr><tr align="center"><th bgcolor="#CCBBBB"><span>signal</span></th><td colspan="7" bgcolor="lightgray"><br></td><td colspan="9"><span>GDEVE</span></td></tr></tbody></table><span>Like GDEVS</span></td></tr><tr><td align="center"><span>0Ch</span></td><td><span>Display area horizontal direction start setting</span><table cellspacing="0" cellpadding="2" border="1"><tbody><tr bgcolor="#CCBBBB" align="center"><th><span>Bit</span></th><td><span>7</span></td><td><span>6</span></td><td><span>5</span></td><td><span>4</span></td><td><span>3</span></td><td><span>2</span></td><td><span>1</span></td><td><span>0</span></td></tr><tr align="center"><th bgcolor="#CCBBBB"><span>signal</span></th><td bgcolor="lightgray"><br></td><td colspan="7"><span>GDEHS</span></td></tr></tbody></table><span>0 to 50 h </span><br><span>Horizontal 640 dots 8 dots Unit 320 dots 4 dots unit</span></td></tr><tr><td align="center"><span>0Dh</span></td><td><span>Display area horizontal direction stop setting</span><table cellspacing="0" cellpadding="2" border="1"><tbody><tr bgcolor="#CCBBBB" align="center"><th><span>Bit</span></th><td><span>7</span></td><td><span>6</span></td><td><span>5</span></td><td><span>4</span></td><td><span>3</span></td><td><span>2</span></td><td><span>1</span></td><td><span>0</span></td></tr><tr align="center"><th bgcolor="#CCBBBB"><span>signal</span></th><td bgcolor="lightgray"><br></td><td colspan="7"><span>GDEHE</span></td></tr></tbody></table><span>Same as GDEHS</span></td></tr><tr><td align="center"><span>0Eh</span></td><td><span>Display mode switching</span><table cellspacing="0" cellpadding="2" border="1"><tbody><tr bgcolor="#CCBBBB" align="center"><th><span>Bit</span></th><td><span>7</span></td><td><span>6</span></td><td><span>5</span></td><td><span>4</span></td><td><span>3</span></td><td><span>2</span></td><td><span>1</span></td><td><span>0</span></td></tr><tr align="center"><th bgcolor="#CCBBBB"><span>signal</span></th><td><span>EX</span></td><td><span>0</span></td><td><span>0</span></td><td><span><span style="text-decoration-line:overline">4C</span></span></td><td><span>256C</span></td><td><span>V200</span></td><td><span>H640</span></td><td><span>PRI</span></td></tr></tbody></table><small><br></small><table cellspacing="0" cellpadding="2" border="1"><tbody><tr><th bgcolor="#FFFFEE"><span>EX</span></th><td><span>Standard VRAM / Extended VRAM Selection</span></td><td><span>0: Standard VRAM </span><br><span>1: Extended VRAM</span></td></tr><tr><th bgcolor="#FFFFEE"><span><span style="text-decoration-line:overline">4C</span></span></th><td><span>4 color mode </span><br><span>(Only in 640 x 400 mode)</span></td><td><span>0: 4 color mode </span><br><span>1: 16 color or 256 color mode</span></td></tr><tr><th bgcolor="#FFFFEE"><span>256C</span></th><td><span>256 colors (8 planes simultaneous output) mode</span></td><td><span>0: 16 color mode </span><br><span>1: 256 color mode</span></td></tr><tr><th bgcolor="#FFFFEE"><span>V200</span></th><td><span>Number of vertical lines</span></td><td><span>0: 400 line </span><br><span>1: 200 line</span></td></tr><tr><th bgcolor="#FFFFEE"><span>H640</span></th><td><span>Number of horizontal dots</span></td><td><span>0: 320 dots </span><br><span>1: 640 dots</span></td></tr><tr><th bgcolor="#FFFFEE"><span>PRI</span></th><td><span>Priority when overlapping two screens </span><br><span>(320 x 200 only in 16 color mode · </span><br><span>Specify 1 in other modes)</span></td><td><span>0: Young screen with the number at the back </span><br><span>1: Young number screen is toward you</span></td></tr><tr></tr></tbody></table></td></tr><tr><td align="center"><span>0Fh</span></td><td><span>Horizontal dot scroll amount within the scroll area</span><table cellspacing="0" cellpadding="2" border="1"><tbody><tr bgcolor="#CCBBBB" align="center"><th><span>Bit</span></th><td><span>7</span></td><td><span>6</span></td><td><span>5</span></td><td><span>4</span></td><td><span>3</span></td><td><span>2</span></td><td><span>1</span></td><td><span>0</span></td></tr><tr align="center"><th bgcolor="#CCBBBB"><span>signal</span></th><td colspan="5" bgcolor="lightgray"><br></td><td colspan="3"><span>HSCRL</span></td></tr></tbody></table><span>Horizontal scroll amount 0 to 7 in 1 dot unit </span><br><span>A specified number of white pixels are inserted from the left edge of the screen, and the screen shifts to the right by that amount (scrolls) </span><br><span>Therefore, it is necessary to hide the left end from the display area </span><br><span>In 320x200 2 screen mode and 256 color mode, this function can be used only for screens 0 and 2, so it is practically impossible to scroll smoothly</span></td></tr><tr><td align="center"><span>10h, 11h</span></td><td><span>Top left address of screen</span><table cellspacing="0" cellpadding="2" border="1"><tbody><tr bgcolor="#CCBBBB" align="center"><th><span>Port</span></th><td colspan="8"><span>11h</span></td><td colspan="8"><span>10 h</span></td></tr><tr bgcolor="#CCBBBB" align="center"><th><span>Bit</span></th><td><span>7</span></td><td><span>6</span></td><td><span>5</span></td><td><span>4</span></td><td><span>3</span></td><td><span>2</span></td><td><span>1</span></td><td><span>0</span></td><td><span>7</span></td><td><span>6</span></td><td><span>5</span></td><td><span>4</span></td><td><span>3</span></td><td><span>2</span></td><td><span>1</span></td><td><span>0</span></td></tr><tr align="center"><th bgcolor="#CCBBBB"><span>signal</span></th><td bgcolor="lightgray"><br></td><td colspan="15"><span>SAD 0</span></td></tr></tbody></table></td></tr><tr><td align="center"><span>12h, 13h</span></td><td><span>Scroll wrapping address</span><table cellspacing="0" cellpadding="2" border="1"><tbody><tr bgcolor="#CCBBBB" align="center"><th><span>Port</span></th><td colspan="8"><span>13h</span></td><td colspan="8"><span>12h</span></td></tr><tr bgcolor="#CCBBBB" align="center"><th><span>Bit</span></th><td><span>7</span></td><td><span>6</span></td><td><span>5</span></td><td><span>4</span></td><td><span>3</span></td><td><span>2</span></td><td><span>1</span></td><td><span>0</span></td><td><span>7</span></td><td><span>6</span></td><td><span>5</span></td><td><span>4</span></td><td><span>3</span></td><td><span>2</span></td><td><span>1</span></td><td><span>0</span></td></tr><tr align="center"><th bgcolor="#CCBBBB"><span>signal</span></th><td bgcolor="lightgray"><br></td><td colspan="15"><span>SAD 1</span></td></tr></tbody></table><span>When the CRTC's VRAM read address counter reaches this address, the address counter returns to 0000h from the next read</span></td></tr><tr><td align="center"><span>14h, 15h</span></td><td><span>Display address after scroll end line</span><table cellspacing="0" cellpadding="2" border="1"><tbody><tr bgcolor="#CCBBBB" align="center"><th><span>Port</span></th><td colspan="8"><span>15 h</span></td><td colspan="8"><span>14h</span></td></tr><tr bgcolor="#CCBBBB" align="center"><th><span>Bit</span></th><td><span>7</span></td><td><span>6</span></td><td><span>5</span></td><td><span>4</span></td><td><span>3</span></td><td><span>2</span></td><td><span>1</span></td><td><span>0</span></td><td><span>7</span></td><td><span>6</span></td><td><span>5</span></td><td><span>4</span></td><td><span>3</span></td><td><span>2</span></td><td><span>1</span></td><td><span>0</span></td></tr><tr align="center"><th bgcolor="#CCBBBB"><span>signal</span></th><td bgcolor="lightgray"><br></td><td colspan="15"><span>SAD 2</span></td></tr></tbody></table><span>When the display raster reaches the scroll end line, display starts from this address</span></td></tr><tr><td align="center"><span>16h, 17h</span></td><td><span>Scroll end line</span><table cellspacing="0" cellpadding="2" border="1"><tbody><tr bgcolor="#CCBBBB" align="center"><th><span>Port</span></th><td colspan="8"><span>17h</span></td><td colspan="8"><span>16h</span></td></tr><tr bgcolor="#CCBBBB" align="center"><th><span>Bit</span></th><td><span>7</span></td><td><span>6</span></td><td><span>5</span></td><td><span>4</span></td><td><span>3</span></td><td><span>2</span></td><td><span>1</span></td><td><span>0</span></td><td><span>7</span></td><td><span>6</span></td><td><span>5</span></td><td><span>4</span></td><td><span>3</span></td><td><span>2</span></td><td><span>1</span></td><td><span>0</span></td></tr><tr align="center"><th bgcolor="#CCBBBB"><span>signal</span></th><td colspan="7" bgcolor="lightgray"><br></td><td colspan="9"><span>SL1</span></td></tr></tbody></table><span>0 to 190 h (vertical 400 lines) </span><br><span>0 to C 8 h (length 200 lines) </span><br></td></tr><tr><td align="center"><span>18h</span></td><td><span>Screen display register</span><table cellspacing="0" cellpadding="2" border="1"><tbody><tr bgcolor="#CCBBBB" align="center"><th><span>Bit</span></th><td><span>7</span></td><td><span>6</span></td><td><span>5</span></td><td><span>4</span></td><td><span>3</span></td><td><span>2</span></td><td><span>1</span></td><td><span>0</span></td></tr><tr align="center"><th bgcolor="#CCBBBB"><span>signal</span></th><td><span>I1</span></td><td><span>G1</span></td><td><span>R1</span></td><td><span>B1</span></td><td><span>I 0</span></td><td><span>G 0</span></td><td><span>R 0</span></td><td><span>B 0</span></td></tr></tbody></table><span>A plane with a bit of 1 is displayed</span></td></tr></tbody></table><hr style="font-family:'Times New Roman';font-size:medium"></div><div>Zajimavy registr 0Eh pro zmenu rezimu. Chtelo by to vyzkouset s ohledem na vyuzivani pameti a efektu na vystupu</div><div><br></div><div>3) PALETE karta/registr.</div><div><h4 style="font-family:'Times New Roman';font-size:medium"><span>OPN GPIO</span></h4><table style="font-family:'Times New Roman'" cellpadding="2" border="1" bgcolor="white"><tbody><tr bgcolor="#CCBBBB"><th><span>SSG register</span></th><th><span>R / W</span></th><th><span>Description</span></th></tr><tr><td align="center"><span>07h</span></td><td align="center"><span>W</span></td><td><span>I / O setting of I / O ports A and B</span><table cellspacing="0" cellpadding="2" border="1"><tbody><tr bgcolor="#CCBBBB" align="center"><th><span>Bit</span></th><td><span>7</span></td><td><span>6</span></td><td><span>5</span></td><td><span>4</span></td><td><span>3</span></td><td><span>2</span></td><td><span>1</span></td><td><span>0</span></td></tr><tr align="center"><th bgcolor="#CCBBBB"><span>signal</span></th><td><span>IOB</span></td><td><span>IOA</span></td><td colspan="3"><span>noise</span></td><td colspan="3"><span>tone</span></td></tr></tbody></table><small><br></small><table cellspacing="0" cellpadding="2" border="1"><tbody><tr><th bgcolor="#FFFFEE"><span>IOB</span></th><td><span>I / O port B input / output</span></td><td><span>0: Input </span><br><span>1: Output</span></td></tr><tr><th bgcolor="#FFFFEE"><span>IOA</span></th><td><span>I / O port A input / output</span></td><td><span>0: Input </span><br><span>1: Output</span></td></tr></tbody></table><span>For MZ - 2500, set port A as output and port B as input</span></td></tr><tr><td align="center"><span>0Eh</span></td><td align="center"><span>W</span></td><td><span>I / O port A</span><table cellspacing="0" cellpadding="2" border="1"><tbody><tr bgcolor="#CCBBBB" align="center"><th><span>Bit</span></th><td><span>7</span></td><td><span>6</span></td><td><span>5</span></td><td><span>4</span></td><td><span>3</span></td><td><span>2</span></td><td><span>1</span></td><td><span>0</span></td></tr><tr align="center"><th bgcolor="#CCBBBB"><span>signal</span></th><td><span>VACL</span></td><td><span>VOE</span></td><td><span>VBUSY</span></td><td><span>VDATA</span></td><td><span>MOUSE</span></td><td><span><span style="text-decoration-line:overline">PLT</span></span></td><td><span>DRSEL</span></td><td><span>READYA</span></td></tr></tbody></table><small><br></small><table cellspacing="0" cellpadding="2" border="1"><tbody><tr><th bgcolor="#FFFFEE"><span>VACL</span></th><td><span>Voice board reset bit</span></td><td><span>0: Normal operation </span><br><span>1: Reset the voice board</span></td></tr><tr><th bgcolor="#FFFFEE"><span>VOE</span></th><td><span>Voice board ROM specification</span></td><td><span>0: Internal ROM </span><br><span>1: External ROM</span></td></tr><tr><th bgcolor="#FFFFEE"><span>VBUSY</span></th><td colspan="2"><span>Voice board handshake bit</span></td></tr><tr><th bgcolor="#FFFFEE"><span>VDATA</span></th><td colspan="2"><span>Voice board transmission data</span></td></tr><tr><th bgcolor="#FFFFEE"><span>MOUSE</span></th><td><span>SIO B channel function selection</span></td><td><span>0: RS-232C (9 pin) </span><br><span>1: Mouse</span></td></tr><tr><th bgcolor="#FFFFEE"><span><span style="text-decoration-line:overline">PLT</span></span></th><td><span>4096 color palette board output selection</span></td><td><span>0: 4096 color Palette board Select output </span><br><span>1: Select main unit output</span></td></tr><tr><th bgcolor="#FFFFEE"><span>The DRSEL</span></th><td><span>FDD drive number change</span></td><td><span>0: Built-in FDD is 0, 1 / external FDD is 2, 3 </span><br><span>1: External FDD is 0, 1 / Built-in FDD is 2, 3</span></td></tr><tr><th bgcolor="#FFFFEE"><span>READYA</span></th><td colspan="2"><span>RS-232C RR signal (D-Sub 25 pin connector No. 11 pin)</span></td></tr></tbody></table></td></tr><tr><td align="center"><span>0Fh</span></td><td align="center"><span>R</span></td><td><span>I / O port B</span><table cellspacing="0" cellpadding="2" border="1"><tbody><tr bgcolor="#CCBBBB" align="center"><th><span>Bit</span></th><td><span>7</span></td><td><span>6</span></td><td><span>5</span></td><td><span>4</span></td><td><span>3</span></td><td><span>2</span></td><td><span>1</span></td><td><span>0</span></td></tr><tr align="center"><th bgcolor="#CCBBBB"><span>signal</span></th><td><span>VACK</span></td><td><span><span style="text-decoration-line:overline">RASTER</span></span></td><td><span><span style="text-decoration-line:overline">80B</span></span></td><td><span><span style="text-decoration-line:overline">2000</span></span></td><td><span><span style="text-decoration-line:overline">ALARM</span></span></td><td><span>CDB</span></td><td><span>CIA</span></td><td><span>CDA</span></td></tr></tbody></table><small><br></small><table cellspacing="0" cellpadding="2" border="1"><tbody><tr><th bgcolor="#FFFFEE"><span>VACK</span></th><td colspan="2"><span>Acknowledge from voice board</span></td></tr><tr><th bgcolor="#FFFFEE"><span><span style="text-decoration-line:overline">RASTER</span></span></th><td><span>Display output mode</span></td><td><span>0: 400 lines (24 kHz) </span><br><span>1: 200 lines (15 kHz)</span></td></tr><tr><th bgcolor="#FFFFEE"><span><span style="text-decoration-line:overline">80B</span></span></th><td><span>MZ-80B mode</span></td><td><span>0: 80 B mode</span></td></tr><tr><th bgcolor="#FFFFEE"><span><span style="text-decoration-line:overline">2000</span></span></th><td><span>MZ-2000 mode</span></td><td><span>0: 2000 mode</span></td></tr><tr><th bgcolor="#FFFFEE"><span><span style="text-decoration-line:overline">ALARM</span></span></th><td><span>RTC ALARM output</span></td><td><br></td></tr><tr><th bgcolor="#FFFFEE"><span>CDB</span></th><td colspan="2"><span>RS-232C CD signal (D-Sub 9 pin connector 9 pin)</span></td></tr><tr><th bgcolor="#FFFFEE"><span>CIA</span></th><td colspan="2"><span>RS-232C CI signal (D-Sub 25 pin connector No. 22 pin)</span></td></tr><tr><th bgcolor="#FFFFEE"><span>CDA</span></th><td colspan="2"><span>RS-232C CD signal (D-Sub 25 pin connector No. 8 pin)<br><br></span></td></tr></tbody></table></td></tr></tbody></table></div><div><br></div><div>Zajimavy registr 0Eh bit <span style="background-color:rgb(255,255,238);font-family:'Times New Roman';font-weight:bold;text-align:center;text-decoration-line:overline">PLT</span><span style="background-color:transparent">, ktery zapina podporu 4096 barev</span></div><div><span style="background-color:transparent"><br></span></div><div><h3 style="color:rgb(0,0,0);font-family:'Times New Roman'"><span>4096 color palette board</span></h3><span style="font-family:'Times New Roman';font-size:medium">16 bit I / O access required</span><span style="font-family:'Times New Roman';font-size:medium"></span><table style="font-family:'Times New Roman'" cellpadding="2" border="1"><tbody><tr bgcolor="#CCBBBB"><th><span>address</span></th><th><span>R / W</span></th><th><span>Description</span></th></tr><tr><td align="center"><span>AEh</span></td><td align="center"><span>W</span></td><td><span>4096 color palette</span><p><span>Address [15: 8]</span></p><table cellspacing="0" cellpadding="2" border="1"><tbody><tr bgcolor="#CCBBBB" align="center"><th><span>Bit</span></th><td><span>15</span></td><td><span>14</span></td><td><span>13</span></td><td><span>12</span></td><td><span>11</span></td><td><span>Ten</span></td><td><span>9</span></td><td><span>8</span></td></tr><tr align="center"><th bgcolor="#CCBBBB"><span>signal</span></th><td colspan="3" bgcolor="lightgray"><br></td><td colspan="4"><span>PALNO</span></td><td><span>G / <span style="text-decoration-line:overline">R B</span></span></td></tr></tbody></table><small><br></small><table cellspacing="0" cellpadding="2" border="1"><tbody><tr><th bgcolor="#FFFFEE" align="left"><span>G / <span style="text-decoration-line:overline">RB</span></span></th><td><span>0: DATA [3: 0] is written in the blue component of the pallet number PALNO, and DATA [7: 4] is written in the red component </span><br><span>1: Write DATA [3: 0] to the green component of the pallet number PALNO</span></td></tr></tbody></table><p></p></td></tr></tbody></table><span style="font-family:'Times New Roman';font-size:medium">The validity / invalidity of the pallet board is controlled by the OPO IOA [2]</span><span style="background-color:transparent"><br></span></div><div><span style="font-family:'Times New Roman';font-size:medium"><br></span></div><div><font size="3" face="Times New Roman">A pak tady zapisovat do registru PALNO cislo barvy G a RB a pak jeji hodnotu</font></div><div><font size="3" face="Times New Roman"><br></font></div><div><font size="3" face="Times New Roman">4) Mel by nekdo schema a/nebo fotky teto pridavne karty? Ze by se mohla casem pripravit a vyrobit replika. samozrejme by to chtelo mit v MZ-2500 ten pridavny domecek, ktery by se mohl taky replikovat.</font></div><div><h3 style="color:rgb(0,0,0);font-family:'Times New Roman'"><span>MZ-1 R 37 640 K EMM</span></h3><span style="font-family:'Times New Roman';font-size:medium">16 bit I / O access required</span><span style="font-family:'Times New Roman';font-size:medium"></span><table style="font-family:'Times New Roman'" cellpadding="2" border="1"><tbody><tr bgcolor="#CCBBBB"><th><span>address</span></th><th><span>R / W</span></th><th><span>Description</span></th></tr><tr><td align="center"><span>ACh</span></td><td align="center"><span>W</span></td><td><span>Write address latch </span><br><span>EMM address [19: 16] = {A15 - A8}, EMM address [15: 8] = {D7 - D0}</span></td></tr><tr><td rowspan="2" align="center"><span>ADh</span></td><td align="center"><span>R</span></td><td><span>Reading data </span><br><span>EMM address [7: 0] = {A15 - A8}, data = {D7 - D0}</span></td></tr><tr><td align="center"><span>W</span></td><td><span>Write data </span><br><span>EMM address [7: 0] = {A15 - A8}, data = {D7 - D0}</span></td></tr></tbody></table><span style="font-family:'Times New Roman';font-size:medium">* There is no auto increment of the address</span><span style="background-color:transparent"><br></span></div><div><br></div><div>Tak to bylo pro definovani par takovych bodu, kterymi by jsme se mohli zabyvat a urceni mista, kde je sdilet.</div><div><br></div><div>Mikes</div><div><br></div><div><br></div></blockquote></body></html>